Tensilica D2 Model

Description

Tensilica Comms DSP ConnX D2

The ConnX D2 DSP engine is a click-box option for Tensilica's benchmark-breaking Xtensa LX processor technology. The ConnX D2 option adds dual 16-bit multiply-accumulate (MAC) units and a 40-bit register file to the base RISC architecture of the Xtensa LX processor. The ConnX D2 engine utilizes two-way SIMD (single instruction, multiple data) instructions to provide high performance on vectorizable C code. It also delivers dual-MAC performance using 64-bit VLIW (very long instruction word) instructions for code that cannot be vectorized.

The ConnX D2 DSP engine delivers outstanding 16-bit fixed point "out of the box" performance on compiled C code, without the need for assembly code optimization. This allows SOC development teams to have greater flexibility in resource allocation as well as the ability to quickly change algorithms. C code optimized with TI C6x or ITU C intrinsic functions compiles directly to the ConnX D2 instruction set, allowing developers to benefit from pre-existing TI and ITU code bases.

This model is a performance optimized instruction set representation of the processor capable of operating in both cycle accurate and turbo modes. The model integrates directly into SoC Designer Plus virtual prototype environment. This enables designers to perform architectural analysis, performance optimization and pre-silicon software debug.