Tensilica 106Micro Model

Description

Tensilica Diamond 106Micro

The Diamond Standard 106Micro CPU is a cache-less 32-bit controller ideal for designers looking for a basic 32-bit controller, particularly for those migrating up from an 8- or 16-bit controller. Designed for applications with requirements for minimal size and low power, the Diamond Standard 106Micro controller enables SOC architects to quickly integrate this efficient CPU in their designs.

Although the Diamond 106Micro is extremely small, it employs a 5-stage pipeline so it can achieve 650 MHz in 65gp process and up to 900 MHz in 45gs process technology. By modelessly switching between 24- and 16-bit narrow instructions, it achieves much higher code density than other 32/16-bit architectures.

This model is a performance optimized instruction set representation of the processor capable of operating in both cycle accurate and turbo modes. The model integrates directly into SoC Designer Plus virtual prototype environment. This enables designers to perform architectural analysis, performance optimization and pre-silicon software debug.