Tensilica 212GP Model
Description
Tensilica Diamond 212Mini
The Diamond Standard 212GP CPU is a high-performance, fully synthesizable 32-bit
RISC core. It is area and power efficient with a local memory architecture that
provides outstanding flexibility and performance. Designers can take advantage of
Tensilica's lockable cache and attach any size single-cycle instruction or data
SRAM up to 128Kbytes.
Since the Diamond 212GP's target applications are controller related, interrupt
options are extremely important. The Diamond 212GP includes a non-maskable interrupt
for critical system events and six levels of interrupt priorities from a combination
of external, software and timing interrupts. This eases the development of software
interrupt handlers and external interrupt priority hardware design.
This model is a performance optimized instruction set representation of the processor
capable of operating in both cycle accurate and turbo modes. The model integrates
directly into SoC Designer Plus virtual prototype environment. This enables designers
to perform architectural analysis, performance optimization and pre-silicon software
debug.