Tensilica 233L Model

Description

Tensilica Diamond 233L

The Diamond Standard 233L is a high-performance, fully synthesizable 32-bit RISC core. It is area and power efficient with a local memory architecture that provides outstanding flexibility and performance, with a full-featured Memory Management Unit (MMU) for application processing using operating systems such as Linux. The caches are 16Kbyte instruction and data, 4-way set associative.

The MMU provides instruction and data Translation Lookaside Buffers (TLBs), which manage virtual-to-physical address mapping. In addition to address translation, the MMU provides four different privilege levels (for memory protection), variable page sizes and multiple access modes. Combining the MMU with a flexible interrupt architecture and high performance, the Diamond 233L can easily meet the needs of a complex system running numerous operations.

This model is a performance optimized instruction set representation of the processor capable of operating in both cycle accurate and turbo modes. The model integrates directly into SoC Designer Plus virtual prototype environment. This enables designers to perform architectural analysis, performance optimization and pre-silicon software debug.