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ARM PL351 Model

Description

AXI Configurable Single NAND interface Memory Controller


SoC Designer
PL351 Cycle Model
Description The PL351 model is compiled directly from ARM's register transfer level (RTL) code and maintains 100% functional accuracy. The model integrates directly with ARM’s SoC Designer virtual prototype. This enables designers to perform accurate architectural analysis, performance optimization and pre-silicon firmware debug.
Performance Analysis Kits
Revisions r2p1
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