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Arm L2C-310 Model

Description

Level 2 Cache Controller


SoC Designer
L2C-310 Cycle Model
Description The L2C-310 model is compiled directly from Arm's register transfer level (RTL) code and maintains 100% functional accuracy. The model integrates directly with Arm's SoC Designer virtual prototype. This enables designers to perform accurate architectural analysis, performance optimization and pre-silicon firmware debug.
Performance Analysis Kits
Revisions r3p2
Download
IP Link Documentation
Documentation (Login Required)
Capabilities Fast Model,Swap & Play