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Arm GIC-600 Model

Description

The GIC-600 is a generic interrupt controller, that handles interrupts from peripherals to the cores and between cores. The GIC-600 supports a distributed micro-architecture containing several individual blocks that can are used in combination to provide a flexible GIC implementation. The implementation scales from a single core to coherent (unified and consistent) multichip environments containing up to 16 chips of up to 512 cores each.


SoC DesignerSystemC ModelSynopsys PA
GIC-600 Cycle Model
Description The GIC-600 model is compiled directly from Arm's register transfer level (RTL) code and maintains 100% functional accuracy. The model integrates directly with Arm's SoC Designer virtual prototype. This enables designers to perform accurate architectural analysis, performance optimization and pre-silicon firmware debug.
Performance Analysis Kits
Revisions r0p2
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