Arm Cortex A65AE Model

Description

The Cortex A65AE core is a power-efficient, mid-range, throughput computing oriented, simultaneously multi-threaded (SMT) core that implements the Aarch64 execution state of the ARMv8-A architecture.

The Cortex A65AE core has two modes of operation:

* Split mode, where the cores in each core pair operate independently of each other.
* Lock mode, where one of the cores in a core pair functions as a redundant copy of the primary function core.

The Cortex A65AE model includes the DynamIQ Shared Unit-AE (DSU-AE). This DSU-AE integrates multiple Cortex A65AE cores with an L3 memory system, control logic, and external interfaces to form a multicore cluster. The Cortex A65AE model supports 2, 4, 6 or 8 cores in the cluster.

DSU-AE r0p0-00eac0 supports Cortex A65AE r0p0-00eac0.




SystemC ModelSynopsys PA
Cortex A65AE SystemC Model
Description The Cortex A65AE model is compiled directly from Arm register transfer level (RTL) code and maintains 100% functional accuracy. The model integrates directly into any IEEE 1666 compliant SystemC environment.
Special Note The Cycle Models Package contains a model with signal level SystemC wrappers. You can download CPAKs from Arm System Exchange. For more information refer to the SystemC Cycle Model User Guide.
Performance Analysis Kits
Revisions r0p0
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