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Arm CCI-550 Model

Description

The ARMĀ® CoreLinkā„¢ CCI-550 Cache Coherent Interconnect offers a scalable and configurable interconnect which enables SoC designers to meet the performance goals with the smallest possible area and power.


SoC DesignerSystemC ModelSynopsys PA
CCI-550 Cycle Model
Description The CCI-550 model is compiled directly from Arm's register transfer level (RTL) code and maintains 100% functional accuracy. The model integrates directly with Arm's SoC Designer virtual prototype. This enables designers to perform accurate architectural analysis, performance optimization and pre-silicon firmware debug.
Performance Analysis Kits
Revisions r1p0, r0p2
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